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| E n n n n n n n 12.0 V 5% V PP 5 VOLT BULK ERASE FLASH MEMORY 28F010 and 28F020 (x8) Flash Electrical Chip-Erase 1-Mbit: 1 Second Typical Chip-Erase 2-Mbit: 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm 10 s Typical Byte-Program 1-Mbit: 1 Second Chip-Program 2-Mbit: 2 Second Chip-Program 100,000 Erase/Program Cycles High-Performance Read 90 ns Maximum Access Time CMOS Low Power Consumption 10 mA Typical Active Current 50 A Typical Standby Current 0 Watts Data Retention Power Integrated Program/Erase Stop Timer n n n n Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface Noise Immunity Features 10% VCC Tolerance Maximum Latch-Up Immunity through EPI Processing ETOXTM Nonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience JEDEC-Standard Pinouts 32-Pin Plastic Dip 32-Lead PLCC 32-Lead TSOP (See Packaging Spec., Order #231369) n Extended Temperature Options The Intel(R) 5 Volt Bulk Erase CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F010 and 28F020 add electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-board during subassembly test; in-system during final test; and in-system after sale. The 28F010 and 28F020 increase memory flexibility, while contributing to time and cost savings. The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of eight bits. Similarly, the 28F020 is a 2048 kilobit nonvolatile memory organized as 262,144 bytes of eight bits. Both devices are offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs. Extended erase and program cycling capability is designed into Intel(R) ETOXTM (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the 28F010 and 28F020 perform 100,000 erase and program cycles--well within the time limits of the quickpulse programming and quick-erase algorithms. The Intel 28F010 and 28F020 employ advanced CMOS circuitry for systems requiring high-performance access speeds, low power consumption, and immunity to noise. Its 90 ns access time provides zero waitstate performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address and data pins, from -1 V to VCC + 1 V. With Intel ETOX process technology base, the 28F010 and 28F020 build on years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness. December 1998 Order Number: 290663-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F010 and 28F020 may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 8021-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com Copyright (c) Intel Corporation 1996, 1997, 1998. * Third-party brands and names are the property of their respective owners. E 28F010/28F020 CONTENTS PAGE PAGE 4.5 DC Characteristics--28F020--TTL/NMOS Compatible--Commercial Products .......... 22 4.6 DC Characteristics--28F010--CMOS Compatible--Commercial Products .......... 24 4.7 DC Characteristics--28F020--CMOS Compatible--Commercial Products .......... 25 4.8 DC Characteristics--28F010--TTL/NMO Compatible--Extended Temperature Products ................................................... 27 4.9 DC Characteristics--28F020--TTL/NMO Compatible--Extended Temperature Products ................................................... 29 4.10 DC Characteristics--28F010--CMOS Compatible--Extended Temperature Products ................................................... 31 4.11 DC Characteristics--28F020--CMOS Compatible--Extended Temperature Products ................................................... 32 4.12 AC Characteristics--28F010--Read-Only Operation--Commercial and Extended Temperature Products .............................. 35 4.13 AC Characteristics--28F020--Read Only Operations--Commercial and Extended Temperature Products .............................. 36 4.14 AC Characteristics--28F010-- Write/Erase/Program Only Operation-- Commercial and Extended Temperature Products ................................................... 38 4.15 AC Characteristics--28F020-- Write/Erase/Program Only Operation-- Commercial and Extended Temperature Products ................................................... 39 4.16 AC Characteristics--28F010--Alternative CE#-Controlled Write--Commercial and Extended Temperature ............................. 44 4.17 AC Characteristics--28F020--Alternate CE# Controlled Writes--Commercial and Extended Temperature Products .............. 45 4.18 Erase and Programming Performance ..... 46 5.0 ORDERING INFORMATION ......................... 47 6.0 ADDITIONAL INFORMATION....................... 47 1.0 APPLICATIONS.............................................. 5 2.0 PRINCIPLES OF OPERATION....................... 9 2.1 Integrated Stop Timer .................................. 9 2.2 Write Protection ......................................... 10 2.2.1 Bus Operations ................................... 10 2.2.1.1 Read ............................................ 10 2.2.1.2 Output Disable ............................. 10 2.2.1.3 Standby........................................ 11 2.2.1.4 Intelligent Identifier Operation....... 11 2.2.1.5 Write............................................. 11 2.2.2 Command Definitions.......................... 11 2.2.2.1 Read Command ........................... 12 2.2.2.2 Intelligent Identifier Command ...... 12 2.2.2.3 Set-Up Erase/Erase Commands .. 13 2.2.2.4 Erase Verify Command ................ 13 2.2.2.5 Set-Up Program/Program Commands.................................. 13 2.2.2.6 Program Verify Command ............ 13 2.2.2.7 Reset Command .......................... 14 2.2.3 Extended Erase/Program Cycling ....... 14 2.2.4 Quick-Pulse Programming Algorithm .. 14 2.2.5 Quick-Erase Algorithm ........................ 14 3.0 DESIGN CONSIDERATIONS ....................... 17 3.1 Two-Line Output Control............................ 17 3.2 Power Supply Decoupling.......................... 17 3.3 VPP Trace on Printed Circuit Boards .......... 17 3.4 Power-Up/Down Protection........................ 17 3.5 5 Volt Bulk Erase Power Dissipation.......... 17 4.0 ELECTRICAL SPECIFICATIONS ................. 19 4.1 Absolute Maximum Ratings ....................... 19 4.2 Operating Conditions ................................. 19 4.3 Capacitance............................................... 19 4.4 DC Characteristics--28F010--TTL/NMOS Compatible--Commercial Products .......... 20 3 28F010/28F020 E REVISION HISTORY Description Number -001 This document combines datasheets for the 28F010 (order 290207) and 28F020 (order 290245), bulk erase devices. 4 E 1.0 APPLICATIONS The Intel 28F010 and 28F020 flash memories provide nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/ reprogram cycles. These features make the 28F010 and 28F020 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and data tables are required, the 28F010 and 28F020 reprogrammability and nonvolatility make them the obvious and ideal replacements for EPROM. Primary applications and operating systems stored in flash eliminate the slow disk-to-DRAM download process. This results in dramatic enhancement of performance and substantial reduction of power consumption--a consideration particularly important in portable equipment. Flash memory increases flexibility with electrical chip erasure and in-system update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as revisions are made. In diskless workstations and terminals, network traffic reduces to a minimum and systems are instant-on. Reliability exceeds that of electromechanical media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue if boot code, operating systems, communication protocols and primary applications are flash resident in each terminal. For embedded systems that rely on dynamic RAM/disk for main system memory or nonvolatile backup storage, the 28F010 and 28F020 flash memories offer a solid state alternative in a minimal form factor. The 28F010 and 28F020 provide higher performance, lower power consumption, instant-on capability, and allows an "eXecute in place" (XIP) memory hierarchy for code and data table reading. Additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail. The need for code updates pervades all phases of a system's life--from prototyping to system manufacture to after sale service. The electrical chip-erasure and reprogramming ability of the 28F010 and 28F020 allow in-circuit alterability; this eliminates unnecessary handling and less reliable 28F010/28F020 socketed connections, while adding greater test, manufacture, and update flexibility. Material and labor costs associated with code changes increases at higher levels of system integration--the most costly being code updates after sale. Code "bugs," or the desire to augment system functionality, prompt after sale code updates. Field revisions to EPROM-based code requires the removal of EPROM components or entire boards. With the 28F010 and 28F020, code updates are implemented locally via an edge connector, or remotely over a communication link. For systems currently using a high-density static RAM/battery configuration for data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. The concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a considerable cost advantage over static RAM. Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with data accumulation and recording needs. Electrical chip-erasure gives the designer a "blank slate" in which to log or record data. Data can be periodically off-loaded for analysis and the flash memory erased producing a new "blank slate." A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F020s tied to the 80C186 system bus. The 228F010 and 28F020 architecture minimize interface circuitry needed for complete incircuit updates of memory contents. The outstanding feature of the TSOP (Thin Small Outline Package) is the 1.2 mm thickness. TSOP is particularly suited for portable equipment and applications requiring large amounts of flash memory. With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility, the 28F010 and 28F020 offer advantages to the alternatives: EPROMs, EEPROMs, battery backed static RAM, or disk. EPROM-compatible read specifications, straightforward interfacing, and incircuit alterability offers designers unlimited flexibility to meet the high standards of today's designs. 5 28F010/28F020 E DQ0 - DQ7 Erase Voltage Switch To Array Source Input/Output Buffers State Control Command Register Integrated Stop Timer PGM Voltage Switch Chip Enable Output Enable Logic STB Data Latch STB Address Latch Y-Decoder Y-Gating VCC VSS VPP WE# CE# OE# A0 - A17 X-Decoder 2,097,152 Bit Cell Matrix 290207-1 Figure 1. 28F020 Block Diagram 6 E Table 1. Pin Description Symbol A0-A16 DQ0-DQ7 Type INPUT INPUT/OUTPUT Name and Function CE# INPUT OE# WE# INPUT INPUT 28F010/28F020 ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. 28F010: A[0-16], 28F020: A[0-17] DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs data during memory read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Gates the devices output through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the control register and the array. Write enable is active low. Addresses are latched on the falling edge and data is latched on the rising edge of the WE# pulse. Note: With VPP 6.5 V, memory contents cannot be altered. VPP VCC VSS NC ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing the entire array, or programming bytes in the array. DEVICE POWER SUPPLY (5 V 10%) GROUND NO INTERNAL CONNECTION to device. Pin may be driven or left floating. 7 28F010/28F020 E WE# VCC VPP 31 30 29 28 27 WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 VSS DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 N28F010 32-LEAD PLCC 0.450" X 0.550" TOP VIEW A17 for 28F020 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 NC OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3 A12 A15 A16 32 Vcc A17 for 28F020 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 P28F010 26 32-LEAD 8 25 PDIP 9 0.62" x 1.64" 24 10 TOP VIEW 23 11 22 12 13 14 15 16 21 20 19 18 17 A17 for 28F020 A11 A9 A8 A13 A14 NC WE# VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 STANDARD PINOUT E28F010 32-LEAD TSOP 0.31" X 0.72" TOP VIEW 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2. 28F010/28F020 Pin Configurations 8 E VCC 80C186 System Bus A1-A18 DQ8 -DQ15 DQ0 -DQ7 VCC A0-A17 DQ0-DQ7 DQ0-DQ7 VPP A0-A17 VCC VPP Address Decoded Chip Select BHE# WR# A0 RD# OE# WE# OE# 28F020 CE# WE# CE# 28F020 28F010/28F020 VCC 290207-4 Figure 3. 28F020 in a 80C186 System 2.0 PRINCIPLES OF OPERATION Flash memory augments EPROM functionality with in-circuit electrical erasure and reprogramming. The 5 Volt Bulk Erase introduces a command register to manage this new functionality. The command register allows for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility. In the absence of high voltage on the VPP pin, the 5 Volt Bulk Erase is a read-only memory. Manipulation of the external memory control pins yields the standard EPROM read, standby, output disable, and intelligent identifier operations. The same EPROM read, standby, and output disable operations are available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables erasure and programming of the device. All functions associated with altering memory contents--intelligent identifier, erase, erase verify, program, and program verify--are accessed via the command register. Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output data for erase and program verification. 2.1 Integrated Stop Timer Successive command write cycles define the durations of program and erase operations; specifically, the program or erase time durations are normally terminated by associated Program or Erase Verify commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate Verify or Reset command. 9 28F010/28F020 Table 2. 28F010/28F020 Bus Operations Mode Read Output Disable READ-ONLY Standby Intelligent Identifier (Mfr)(2) Intelligent Identifier (Device)(2) Read READ/WRITE Output Disable Standby(5) Write VPP(1) VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH A0 A0 X X VIL VIH A0 X X A0 A9 A9 X X VID(3) VID(3) A9 X X A9 CE# VIL VIL VIH VIL VIL VIL VIL VIH VIL OE# WE# VIL VIH X VIL VIL VIL VIH X VIH VIH VIH X VIH VIH VIH VIH X VIL E DQ0-DQ7 Data Out Tri-State Tri-State Data = 89H Data = B4H Data Out(4) Tri-State Tri-State Data In(6) NOTES: 1. Refer to DC Characteristics. When VPP = VPPL memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other addresses low. 3. VID is the intelligent identifier high voltage. Refer to DC Characteristics. 4. Read operations with VPP = VPPH may access array data or the intelligent identifier codes. 5. With VPP at high voltage, the standby current equals ICC + IPP (standby). 6. Refer to Table 3 for valid data-in during a write operation. 7. X can be VIL or VIH. 2.2 Write Protection 2.2.1 2.2.1.1 BUS OPERATIONS Read The command register is only active when VPP is at high voltage. Depending upon the application, the system designer may choose to make the VPP power supply switchable--available only when memory updates are desired. When VPP = VPPL, the contents of the register default to the Read command, making the 28F010 and 28F020 readonly memories. In this mode, the memory contents cannot be altered. Or, the system designer may choose to "hardwire" VPP, making the high voltage supply constantly available. In this case, all command register functions are inhibited whenever VCC is below the write lockout voltage VLKO. (See Section 3.4, Power-Up/Down Protection.) The 28F010 and 28F020 are designed to accommodate either design practice, and to encourage optimization of the processor memory interface. The two-step program/erase write sequence to the command register provides additional software write protections. 10 The 28F010 and 28F020 have two control functions, both of which must be logically active, to obtain data at the outputs. Chip Enable (CE#) is the power control and should be used for device selection. Output Enable (OE#) is the output control and should be used to gate data from the output pins, independent of device selection. Refer to the AC read timing waveforms. When VPP is high (VPPH), the read operation can be used to access array data, to output the intelligent identifier codes, and to access data for program/erase verification. When VPP is low (VPPL), the read operation can only access the array data. 2.2.1.2 Output Disable With OE# at a logic-high level (VIH), output from the device is disabled. Output pins are placed in a highimpedance state. E 2.2.1.3 2.2.1.4 28F010/28F020 2.2.1.5 Write Standby With CE# at a logic-high level, the standby operation disables most of the 28F010 and 28F020's circuitry and substantially reduces device power consumption. The outputs are placed in a high-impedance state, independent of the OE# signal. If the 28F010 and 28F020 are deselected during erasure, programming, or program/erase verification, the device draws active current until the operation is terminated. Intelligent Identifier Operation Device erasure and programming are accomplished via the command register, when high voltage is applied to the VPP pin. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command. The command register is written by bringing WE# to a logic-low level (VIL), while CE# is low. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. Refer to AC Characteristics--Write/Erase/Program Only Operations and the erase/programming waveforms for specific timing parameters. 2.2.2 COMMAND DEFINITIONS The intelligent identifier operation outputs the manufacturer code (89H) and device code (B4H for 28F010, BDH for 28F020). Programming equipment automatically matches the device with its proper erase and programming algorithms. With CE# and OE# at a logic low level, raising A9 to high voltage VID (see DC Characteristics) activates the operation. Data read from locations 0000H and 0001H represent the manufacturer's code and the device code, respectively. The manufacturer and device codes can also be read via the command register, for instances where the 28F010 and 28F020 are erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location 0000H outputs the manufacturer code (89H). A read from address 0001H outputs the device code (B4H for 28F010, BDH for 28F020). When low voltage is applied to the VPP pin, the contents of the command register default to 00H, enabling read-only operations. Placing high voltage on the VPP pin enables read/write operations. Device operations are selected by writing specific data patterns into the command register. Table 3 defines these 28F010/28F020 register commands. 11 28F010/28F020 Table 3. Command Definitions First Bus Cycle Bus Cycles Req'd 1 3 2 2 2 2 2 E Second Bus Cycle Operation(1) Address(2) Data(3) Read Write Read Write Read Write IA X X PA X X ID 20H EVD PD PVD FFH Command Read Memory Read Intelligent Identifier Codes(4) Set-Up Erase/Erase(5) Erase Verify(5) Set-Up Program/ Program(6) Program Verify(6) Reset(7) Operation(1) Address(2) Write Write Write Write Write Write Write X IA X EA X X X Data(3) 00H 90H 20H A0H 40H C0H FFH NOTES: 1. Bus operations are defined in Table 2. 2. IA = Identifier address: 00H for manufacturer code, 01H for device code. EA = Erase Address: Address of memory location to be read during erase verify. PA = Program Address: Address of memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse. 3. ID = Identifier Data: Data read from location IA during device identification (Mfr = 89H, Device = (B4H for 28F010, BDH for 28F020). EVD = Erase Verify Data: Data read from location EA during erase verify. PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE#. PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command. 4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes. 5. Figure 5 illustrates the 28F010/28F020 Quick-Erase Algorithm flowchart. 6. Figure 4 illustrates the 28F010/28F020 Quick-Pulse Programming Algorithm flowchart. 7. The second bus cycle must be followed by the desired command register write. 2.2.2.1 Read Command While VPP is high, for erasure and programming, memory contents can be accessed via the Read command. The read operation is initiated by writing 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. The default contents of the register upon VPP power-up is 00H. This default value ensures that no spurious alteration of memory contents occurs during the VPP power transition. Where the VPP supply is hardwired to the 28F010 or the 28F020, the device powers-up and remains enabled for reads until the command register contents are changed. 12 Refer to the AC Characteristics--Read-Only Operations and waveforms for specific timing parameters. 2.2.2.2 Intelligent Identifier Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system design practice. The 28F010 and 28F020 contain an intelligent identifier operation to supplement traditional PROMprogramming methodology. The operation is initiated by writing 90H into the command register. Following the command Write, a read cycle from address 0000H retrieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of (B4H for 28F010, BDH for 28F020). To terminate the operation, it is necessary to write another valid command into the register. 2.2.2.3 Set-Up Erase/Erase Commands E 28F010/28F020 In the case where the data read is not FFH, another erase operation is performed. (Refer Section 2.2.2.3, Set-Up Erase/Erase Commands.) Verification then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is complete. The device can be programmed. At this point, the verify operation is terminated by writing a valid command (e.g., Program Set-Up) to the command register. Figure 5, the 28F010/28F020 Quick-Erase Algorithm flowchart, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F010 and 28F020. Refer to AC Characteristics--Write/Erase/Program Only Operations and waveforms for specific timing parameters. 2.2.2.5 Set-Up Program/Program Commands Set-Up Erase is a command-only operation that stages the device for electrical erasure of all bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip-erasure, the Erase command (20H) must again be written to the register. The erase operation begins with the rising edge of the WE# pulse and terminates with the rising edge of the next WE# pulse (i.e., Erase Verify command). This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when high voltage is applied to the pin. In the absence of this high voltage, memory contents are protected against erasure. Refer to AC Characteristics--Write/Erase/Program Only Operations and waveforms for specific timing parameters. 2.2.2.4 Erase Verify Command Set-up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register performs the set-up operation. Once the program set-up operation is performed, the next WE# pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE# pulse. Data is internally latched on the rising edge of the WE# pulse. The rising edge of WE# also begins the programming operation. The programming operation terminates with the next rising edge of WE#, used to write the Program Verify command. Refer to AC Characteristics--Write/Erase/Program Only Operations and Waveforms for specific timing parameters. 2.2.2.6 Program Verify Command The Erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H into the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the WE# pulse. The register write terminates the erase operation with the rising edge of its WE# pulse. The 5 Volt Bulk Erase applies an internallygenerated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased. The Erase Verify command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. The 5 Volt Bulk Erase is programmed on a byte-bybyte basis. Byte programming may occur sequentially or at random. Following each programming operation, the byte just programmed must be verified. The program verify operation is initiated by writing C0H into the command register. The register write terminates the programming operation with the rising edge of its WE# pulse. The program verify operation stages the device for verification of the byte last programmed. No new address information is latched. 13 28F010/28F020 The 5 Volt Bulk Erase applies an internallygenerated margin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison between the programmed byte and true data means that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 5, the 28F010/28F020 Quick-Pulse Programming Algorithm flowchart, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC Characteristics--Write/Erase/Program Only Operations and waveforms for specific timing parameters. 2.2.2.7 Reset Command and quick- erase algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program the device. 2.2.4 QUICK-PULSE PROGRAMMING ALGORITHM E A Reset command is provided as a means to safely abort the Erase or Program command sequences. Following either Set-Up command (Erase or Program) with two consecutive writes of FFH will safely abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. 2.2.3 EXTENDED ERASE/PROGRAM CYCLING The quick-pulse programming algorithm uses programming operations of 10 s duration. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes verify on the first or second operation. The entire sequence of programming and byte verification is performed with VPP at high voltage. Figure 4 illustrates the 28F010/28F020 Quick-Pulse Programming Algorithm flowchart. 2.2.5 QUICK-ERASE ALGORITHM Intel's quick-erase algorithm yields fast and reliable electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the quick-pulse programming algorithm, to simultaneously remove charge from all bits in the array. Erasure begins with a read of memory contents. The 5 Volt Bulk Erase is erased when shipped from the factory. Reading FFH data from the device would immediately be followed by device programming. For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (Data = 00H). This is accomplished, using the quick-pulse programming algorithm, in approximately two seconds. Erase execution then continues with an initial erase operation. Erase verification (data = FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is encountered. With each erase operation, an increasing number of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the 28F010/28F020 Quick-Erase Algorithm flowchart. EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled--an expensive solution. Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electric field is onetenth that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak electric field during erasure is approximately 2 MV/cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failure. The 5 Volt Bulk Erase is capable or 100,000 program/erase cycles. The device is programmed and erased using Intel's quick-pulse programming 14 E Start Programming (4) Apply VPPH (1) 28F010/28F020 Bus Operation Standby Command Comments Wait for VPP Ramp to VPPH(1) PLSCNT = 0 Initialize Pulse-Count Set-Up Program Program Write Set-Up Program Cmd Write Program Cmd (A/D) Write Write Data = 40H Valid Address/Data Duration of Program Operation (tWHWH1 ) Standby Time Out 10 s Write Program Verify Cmd Time Out 6 s Read Data from Device N Verify Data N Inc PLSCNT =25? Y Y Increment Address N Last Address? Y Write Read Cmd Apply VPPL (1) Standby Write Read Standby Write Program Verify(2) Data = C0H; Stops Program Operations(3) tWHGL Read Byte to Verify Programming Stand-by Read Compare Data Output to Data Expected Data = 00H, Resets the Register for Read Operations Wait for VPP Ramp to VPPL(1) Apply VPPL (1) Programming Completed Program Error 0207_04 NOTES: 1. See DC Characteristics for the value of VPPH and VPPL. 2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command. 3. Refer to Principles of Operation. 4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device. Figure 4. 28F010/28F020 Quick-Pulse Programming Algorithm 15 28F010/28F020 E Start Erasure (4) Bus Operation Command Comments Entire Memory Must = 00H Before Erasure Use Quick-Pulse Programming Algorithm (Figure 4) Standby Wait for VPP Ramp to VPPH (1) Y Data = 00H? N Program All Bytes to 00H Apply VPPH (1) ADDR = 00H PLSCNT = 0 Write Erase Set-Up Cmd Write Erase Cmd Time Out 10 ms Set-Up Erase Erase Initialize Addresses and Pulse-Count Write Write Stand-by Erase (2) Verify Data = 20H Data = 20H Duration of Erase Operation (tWHWH2 ) Addr = Byte to Verify; Data = A0H; Stops Erase Operation(3) tWHGL Read Byte to Verify Erasure Write Erase Verify Cmd Time Out 6 s Read Data from Device N N Data = FFH? Y N Increment Addr Last Address? Y Write Read Cmd Inc PLSCNT = 1000? Y Write Standby Read Standby Compare Output to FFH Increment Pulse-Count Write Read Data = 00H, Resets the Register for Read Operations Standby Apply VPPL (1) Erasure Completed Apply VPPL (1) Wait for VPP Ramp to VPPL (1) Erase Error 0207_05 NOTES: 1. See DC Characteristics for the value of VPPH and VPPL. 2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is written with the Read command. 3. Refer to Principles of Operation. 4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device. Figure 5. 28F010/28F020 Quick-Erase Algorithm 16 E 3.0 3.1 28F010/28F020 DESIGN CONSIDERATIONS Two-Line Output Control 3.3 VPP Trace on Printed Circuit Boards Flash memories are often used in larger memory arrays. Intel provides two read control inputs to accommodate multiple memory connections. Twoline control provides for: a. the lowest possible memory power dissipation and, b. complete assurance that output bus contention will not occur. To efficiently use these two control inputs, an address decoder output should drive chip-enable, while the system's read signal controls all flash memories and other parallel memories. This assures that only enabled memory devices have active outputs, while deselected devices maintain the low power standby condition. Programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and layout considerations given the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. 3.4 Power-Up/Down Protection The 5 Volt Bulk Erase is designed to offer protection against accidental erasure or programming during power transitions. Upon powerup, the 5 Volt Bulk Erase is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the 5 Volt Bulk Erase ensures that the command register is reset to the read mode on power-up. A system designer must guard against active writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The control register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. 3.2 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers are interested in three supply current (ICC) issues--standby, active, and transient current peaks produced by falling and rising edges of chipenable. The capacitive and inductive loads on the device outputs determine the magnitudes of these peaks. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between VCC and VSS, and between VPP and VSS. Place the high-frequency, low-inherent inductance capacitors as close as possible to the devices. Also, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection, between VCC and VSS. The bulk capacitor will overcome voltage slumps caused by printed circuit board trace inductance, and will supply charge to the smaller capacitors as needed. 3.5 5 Volt Bulk Erase Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases the usable battery life of your system because the 5 Volt Bulk Erase does not consume any power to retain code or data when the system is off. Table 4 illustrates the power dissipated when updating the 5 Volt Bulk Erase. 17 28F010/28F020 E Table 4. 5 Volt Bulk Erase Typical Update Power Dissipation(4) Notes Power Dissipation (Watt-Seconds) 28F010 28F020 0.34 0.37 1.05 1 2 3 0.171 0.136 0.478 Operation Array Program/Program Verify Array Erase/Erase Verify One Complete Cycle NOTES: 1. Formula to calculate typical Program/Program Verify Power = [VPP x # Bytes x typical # Prog Pulses (tWHWH1 x IPP2 typical + tWHGL x IPP4 typical)] + [VCC x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typical + tWHGL x ICC4 typical]. 2. Formula to calculate typical Erase/Erase Verify Power = [VPP (VPP3 typical x tERASE typical + IPP5 typical x tWHGL x # Bytes)] + [VCC (ICC3 typical x tERASE typical + ICC5 typical x tWHGL x # Bytes)]. 3. One Complete Cycle = Array Preprogram + Array Erase + Program. 4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. 18 E 4.0 4.1 28F010/28F020 NOTICE: This is a production datasheet. The specifications are subject to change without notice. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Operating Temperature During Read............................... 0 C to +70 C(1) During Erase/Program ............... 0 C to +70 C(1) Operating Temperature During Read........................... -40 C to +85 C(2) During Erase/Program ........... -40 C to +85 C(2) Temperature Under Bias ........... -10 C to +80 C(1) Temperature Under Bias ........... -50 C to +95 C(2) Storage Temperature ..................-65 C to +125 C Voltage on Any Pin with Respect to Ground.................. -2.0 V to +7.0 V(3) Voltage on Pin A9 with Respect to Ground..............-2.0 V to +13.5 V(3, 4) VPP Supply Voltage with Respect to Ground During Erase/Program ........-2.0 V to +14.0 V(3, 4) VCC Supply Voltage with Respect to Ground.................. -2.0 V to +7.0 V(3) Output Short Circuit Current .....................100 mA(5) *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. NOTES: 1. Operating Temperature is for commercial product as defined by this specification. 2. Operating Temperature is for extended temperature products as defined by this specification. 3. Minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. 4. Maximum DC voltage on A9 or VPP may overshoot to +14.0 V for periods less than 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. 6. See AC Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics. 4.2 Operating Conditions Limits Symbol TA TA VCC VCC Parameter Operating Temperature(1) Operating Temperature(2) VCC Supply Voltage (10%)(6) VCC Supply Voltage (5%)(7) Min 0 -40 4.50 4.75 Max 70 +85 5.50 5.25 Unit C C V V 4.3 Capacitance Limits TA = 25 C, f = 1.0 MHz Symbol CIN COUT Parameter Address/Control Capacitance Output Capacitance Notes 1 1 Min Max 8 12 Unit pF pF Conditions VIN = 0 V VOUT = 0 V NOTE: 1. Sampled, not 100% tested. 19 28F010/28F020 4.4 DC Characteristics--28F010--TTL/NMOS Compatible Commercial Products Limits E Test Conditions Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current or Standby Current Notes 1 1 1 1 1, 2 1, 2 1, 2 1, 2 1 1 Min Typ(3) Max 1.0 10 Unit A A mA mA mA mA mA mA A A VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VIH VCC = VCC Max, CE# = V IL f = 6 MHz, I OUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC VPP VCC 0.3 10 1.0 5.0 5.0 5.0 1.0 30 10 15 15 15 10 90 200 10.0 IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VID VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage 1, 2 1, 2 1, 2 1, 2 -0.5 2.0 8.0 6.0 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 mA mA mA mA V V V V VPP = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA 2.4 11.50 13.00 V 20 E 4.4 Symbol IID VPPL VPPH VLKO 28F010/28F020 DC Characteristics--28F010--TTL/NMOS Compatible Commercial Products (Continued) Limits Parameter A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage Notes 1, 2 0.00 11.40 2.5 Min Typ(3) 90 Max 200 6.5 12.60 Unit A V V V Test Conditions A9 = VID NOTE: Erase/Program are Inhibited when VPP = VPPL NOTES: Sampled, not 100% tested. 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25 C. These currents are valid for all product versions (packages and speeds). 2. Not 100% tested: characterization data available. 3. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. 21 28F010/28F020 4.5 DC Characteristics--28F020--TTL/NMOS Compatible Commercial Products Limits E Test Conditions Symbol ILI ILO ICCS ICC1 Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current Notes 1 1 1 1 Min Typ(3) Max 1.0 10 Unit A A mA mA VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VIH VCC = VCC Max CE# = VIL f = 6 MHz IOUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC VPP VCC 0.3 10 1.0 30 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current, ID Current or Standby Current 1, 2 1, 2 1, 2 1, 2 1 1 1.0 5.0 5.0 5.0 10 15 15 15 10 mA mA mA mA A A 90 200 10 IPP2 IPP3 IPP4 IPP5 VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase- Verify Current 1, 2 1, 2 1, 2 1, 2 8 10 2.0 2.0 30 30 5.0 5.0 mA mA mA mA VPP = VPPH Programming in Progress VPP = VPPH VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress 22 E 4.5 Symbol VIL VIH VOL VOH1 VID IID VPPL VPPH VLKO 28F010/28F020 DC Characteristics--29F020--TTL/NMOS Compatible Commercial Products (Continued) Limits Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage 1, 2 0.00 11.40 2.5 2.4 11.50 90 13.00 200 6.5 12.60 Notes Min -0.5 2.0 Typ(3) Max 0.8 VCC + 0.5 0.45 Unit V V V V V A V V V A9 = VID NOTE: Erase/Program are Inhibited when VPP = VPPL VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA Test Conditions NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25 C. These currents are valid for all product versions (packages and speeds). 2. Not 100% tested: Characterization data available. 3. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. 23 28F010/28F020 4.6 DC Characteristics--28F010--CMOS Compatible Commercial Products Limits E Test Conditions VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VCC 0.2 V VCC = VCC Max, CE# = V IL f = 6 MHz, I OUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current, ID Current or Standby Current Notes 1 1 1 1 1, 2 1, 2 1, 2 1, 2 1 1 Min Typ(3) Max 1.0 10 Unit A A A mA mA mA mA mA A A 50 10 1.0 5.0 5.0 5.0 100 30 10 15 15 15 10 90 200 10 IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VOH2 24 VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.85 VCC VCC - 0.4 1, 2 1, 2 1, 2 1, 2 -0.5 0.7 VCC 8.0 6.0 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 mA mA mA mA V V V V VPP VCC VPP > = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A E 4.6 Symbol VID IID VPPL VPPH VLKO 28F010/28F020 DC Characteristics--28F010--CMOS Compatible Commercial Products (Continued) Limits Parameter A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage 1, 2 0.00 11.40 2.5 Notes Min 11.50 90 Typ(3) Max 13.00 200 6.5 12.60 Unit V A V V V A9 = VID NOTE: Erase/Programs are Inhibited when VPP = VPPL Test Conditions NOTES: Refer to Section 4.4. 4.7 DC Characteristics--28F020--CMOS Compatible Commercial Products Limits Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current Notes 1 1 1 1 50 10 Min Typ(3) Max 1.0 10 100 30 Unit A A A mA Test Conditions VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VCC 0.2 V VCC = VCC Max CE# = VIL f = 6 MHz, IOUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current 1, 2 1, 2 1, 2 1, 2 1 1.0 5.0 5.0 5.0 10 15 15 15 10 mA mA mA mA A 25 28F010/28F020 4.7 DC Characteristics--28F020--CMOS Compatible Commercial Products (Continued) Limits Parameter VPP Read Current, ID Current or Standby Current Notes 1 Min Typ(3) 90 Max 200 Unit A E Test Conditions VPP > VCC VPP VCC VPP = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress Symbol IPP1 10 IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VOH2 VID IID VPPL VPPH VLKO A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage 1, 2 0.00 11.4 0 2.5 VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.85 VCC VCC - 0.4 11.5 0 90 13.00 200 6.5 12.60 V A V V V 1, 2 1, 2 1, 2 1, 2 -0.5 0.7 VCC 8 10 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 mA mA mA mA V V V V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A A9 = VID NOTE: Erase/Programs are Inhibited when VPP = VPPL 26 E 4.8 Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 28F010/28F020 DC Characteristics--28F010--TTL/NMOS Compatible Extended Temperature Products Limits Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current or Standby Current Notes 1 1 1 1 1, 2 1, 2 1, 2 1, 2 1 1 90 0.3 10 1.0 5.0 5.0 5.0 Min Typ(3) Max 1.0 10 1.0 30 30 30 30 30 10 200 10.0 Unit A A mA mA mA mA mA mA A A Test Conditions VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VIH VCC = VCC Max, CE# = V IL f = 6 MHz, I OUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC VPP VCC mA mA mA mA V V V V 13.00 V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VPP = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VID VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage 1, 2 1, 2 1, 2 1, 2 -0.5 2.0 8.0 6.0 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 2.4 11.50 27 28F010/28F020 4.8 DC Characteristics--28F010--TTL/NMOS Compatible Extended Temperature Products (Continued) Limits E Test Conditions Symbol IID VPPL VPPH VLKO Parameter A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage Notes 1, 2 Min Typ(3) 90 Max 500 6.5 12.60 Unit A V V V A9 = VID NOTE: Erase/Program are Inhibited when VPP = VPPL 0.00 11.40 2.5 NOTES: Refer to Section 4.4. 28 E 4.9 Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 28F010/28F020 DC Characteristics--28F020--TTL/NMOS Compatible Extended Temperature Products Limits Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current Notes 1 1 1 1 0.3 10 Min Typ(3) Max 1.0 10 1.0 30 Unit A A mA mA Test Conditions VCC = VCC Max VIN = VCC or VSS VCC= VCC Max VOUT = VCC or VCC = VCC Max CE# = VIH VCC = VCC Max CE# = VIL f = 6 MHz IOUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC VSS VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current, ID Current or Standby Current 1, 2 1, 2 1, 2 1, 2 1 1 1.0 5.0 5.0 5.0 30 30 30 30 10 mA mA mA mA A A 90 200 10 IPP2 IPP3 IPP4 VPP Programming Current VPP Erase Current VPP Program Verify Current 1, 2 1, 2 1, 2 8 10 2.0 30 30 5.0 mA mA mA VPP VCC VPP = VPPH Programming in Progress VPP = VPPH VPP = VPPH Program Verify in Progress 29 28F010/28F020 4.9 DC Characteristics--TTL/NMOS Compatible Extended Temperature Products (Continued) Limits E Unit mA V V V V VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOL = 5.8 mA Test Conditions VPP = VPPH Erase Verify in Progress V A V V V A9 = VID NOTE: Erase/Program are Inhibited when VPP = VPPL Symbol IPP5 VIL VIH VOL VOH1 VID IID VPPL VPPH VLKO Parameter VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage Notes 1, 2 Min Typ(3) 2.0 Max 5.0 0.8 VCC + 0.5 0.45 -0.5 2.0 2.4 11.50 1, 2 0.00 11.40 2.5 90 13.00 500 6.5 12.60 30 E 4.10 Symbol ILI ILO ICCS ICC1 ICC2 ICC3 ICC4 ICC5 IPPS IPP1 28F010/28F020 DC Characteristics--28F010--CMOS Compatible Extended Temperature Products Limits Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VCC Program Verify Current VCC Erase Verify Current VPP Leakage Current VPP Read Current, ID Current or Standby Current Notes 1 1 1 1 1, 2 1, 2 1, 2 1, 2 1 1 90 50 10 1.0 5.0 5.0 5.0 Min Typ(3) Max 1.0 10 100 30 10 30 30 30 10 200 Unit A A A mA mA mA mA mA A A Test Conditions VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VSS VCC = VCC Max CE# = VCC 0.2 V VCC = VCC Max, CE# = V IL f = 10 MHz, I OUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC 10 IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VOH2 VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.85 VCC VCC - 0.4 1, 2 1, 2 1, 2 1, 2 -0.5 0.7 VCC 8.0 6.0 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 mA mA mA mA V V V V VPP VCC VPP = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A 31 28F010/28F020 4.10 DC Characteristics--28F010--CMOS Compatible Extended Temperature Products (Continued) Limits E Test Conditions A9 = VID NOTE: Erase/Programs are Inhibited when VPP = VPPL Symbol VID IID VPPL VPPH VLKO Parameter A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage Notes Min 11.50 Typ(3) Max 13.00 Unit V A V V V 1, 2 0.00 11.40 2.5 90 500 6.5 12.60 NOTE: Refer to Section 4.4. 4.11 DC Characteristics--28F020--CMOS Compatible Extended Temperature Products Limits Symbol ILI ILO ICCS ICC1 Parameter Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current Notes 1 1 1 1 Min Typ(3) Max 1.0 10 Unit A A A mA Test Conditions VCC = VCC Max VIN = VCC or VSS VCC = VCC Max VOUT = VCC or VCC = VCC Max CE# = VCC 0.2 V VCC = VCC Max CE# = VIL f = 6 MHz IOUT = 0 mA Programming in Progress Erasure in Progress VPP = VPPH Program Verify in Progress VSS 50 10 100 50 ICC2 ICC3 ICC4 VCC Programming Current VCC Erase Current VCC Program- Verify Current 1, 2 1, 2 1, 2 1.0 5.0 5.0 10 30 30 mA mA mA 32 E 4.11 Symbol ICC5 IPPS IPP1 IPP2 IPP3 IPP4 IPP5 VIL VIH VOL VOH1 VOH2 VID IID 28F010/28F020 DC Characteristics--28F020--CMOS Compatible Extended Temperature Products (Continued) Limits Parameter VCC Erase Verify Current VPP Leakage Current VPP Read Current, ID Current or Standby Current Notes 1, 2 1 1 90 Min Typ(3) 5.0 Max 30 10 200 Unit mA A A Test Conditions VPP = VPPH Erase Verify in Progress VPP VCC VPP > VCC 10 VPP Programming Current VPP Erase Current VPP Program Verify Current VPP Erase Verify Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.85 VCC VCC - 0.4 A9 Intelligent Identifier Voltage A9 Intelligent Identifier Current 1, 2 11.50 90 13.00 500 V A 1, 2 1, 2 1, 2 1, 2 -0.5 0.7 VCC 8 10 2.0 2.0 30 30 5.0 5.0 0.8 VCC + 0.5 0.45 mA mA mA mA V V V V VPP VCC VPP = VPPH Programming in Progress VPP = VPPH Erasure in Progress VPP = VPPH Program Verify in Progress VPP = VPPH Erase Verify in Progress VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A A9 = VID 33 28F010/28F020 4.11 DC Characteristics--28F020--CMOS Compatible Extended Temperature Products (Continued) Limits E Test Conditions NOTE: Erase/Programs are Inhibited when VPP = VPPL 1.3V Symbol VPPL VPPH VLKO Parameter VPP during Read-Only Operations VPP during Read/Write Operations VCC Erase/Write Lock Voltage Notes Min 0.00 11.40 2.5 Typ(3) Max 6.5 12.60 Unit V V V NOTE: Refer to Section 4.4. 2.4 Input 0.45 2.0 Test Points 0.8 2.0 Output 0.8 0207_06 1N914 RL = 3.3 k Device Under Test Out CL = 100 pF 0207_07 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 6. Testing Input/Output Waveform CL Includes Jig Capacitance Figure 7. AC Testing Load Circuit 34 E 4.12 Symbol tAVAV/tRC tELQV/tCE tGLQV/tOE tELQX/tLZ tEHQZ 28F010/28F020 AC Characteristics--28F010--Read-Only Operations Commercial and Extended Temperature Products Versions Characteristic Read Cycle Time CE# Access Time Notes 28F010-90(1) Min 90 90 90 35 2, 3 2 2, 3 2 2, 4 0 6 0 30 0 6 0 45 0 30 0 6 0 55 0 35 Max 28F010-120(1) 28F010-150(1) Min 120 120 120 50 0 55 Max Min 150 150 150 55 Max Unit ns ns ns ns ns ns ns ns ns s tAVQV/tACC Address Access Time OE# Access Time CE# to Low Z Chip Disable to Output in High Z tGLQX/tOLZ OE# to Output in Low Z tGHQZ/tDF tOH tWHGL Output Disable to Output in High Z Output Hold from Address, CE#, or OE# Change Write Recovery Time before Read NOTES: 1. See AC Input/Output Waveform and AC Testing Load Circuit for testing characteristics. 2. Sampled, not 100% tested. 3. Guaranteed by design. 4. Whichever occurs first. 35 28F010/28F020 4.13 AC Characteristics--28F020--Read Only Operations Commercial and Extended Temperature Products Versions 28F020-90(4) Notes Min 90 90 90 35 2, 3 2 2, 3 2 1, 2 0 6 0 30 0 6 0 45 0 30 0 6 0 55 0 Max E Min 150 Max Unit ns 150 150 50 0 55 ns ns ns ns ns ns 30 ns ns s 50 28F020-120(4) 28F020-150(4) Min 120 120 120 Max Symbol tAVAV/tRC Characteristics Read Cycle Time tELQV/tCE> Chip Enable Access Time tAVQV/tACC Address Access Time tGLQV/tOE tELQX/tLZ tEHQZ Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z tGLQX/tOLZ Output Enable to Output in Low Z tGHQZ/tDF tOH tWHGL Output Disable to Output in High Z Output Hold from Address, CE#, or OE# Change Write Recovery Time before Read NOTES: 1. Whichever occurs first. 2. Sampled, not 100% tested. 3. Guaranteed by design. 4. See High Speed AC Testing Input/Output Waveform (Figure 8) and High Speed AC Testing Load Circuit (Figure 9) for testing characteristics. 5. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics. 36 E 28F010/28F020 290207-9 Figure 8. AC Waveforms for Read Operations 37 28F010/28F020 4.14 AC Characteristics--28F010--Write/Erase/Program Only Operations(1) Commercial and Extended Temperature Products Versions 28F010-90(2) Notes Min 90 0 40 3 55 40 55 40 40 Max 28F010-120(2) 28F010-150(2) Min 120 0 40 Max Min 150 0 40 Max E Unit ns ns ns ns ns s ns ns ns ns Symbol tAVAV/tWC tAVWL/tAS tWLAX/tAH Characteristic Write Cycle Time Address Set-Up Time Address Hold Time tDVWH/tDS Data Set-Up Time tWHDX/tDH tWHGL tGHWL tELWL/tCS tWHEH/tCH tWLWH/tWP Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Write Pulse Width 3 4 10 6 0 15 0 40 55 20 5 5 4 10 9.5 1 10 6 0 15 0 60 10 6 0 15 0 60 tWHWL/tWPH Write Pulse Width High tWHWH1 tWHWH2 tVPEL Duration of Programming Operation Duration of Erase Operation VPP Set-Up Time to Chip Enable Low 20 10 9.5 1 20 10 9.5 1 ns s ms s NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. See AC Input/Output Waveform and AC Testing Load Circuit for testing characteristics. 3. Minimum specification for extended temperature product. 4. Guaranteed by design. 5. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 38 E 4.15 Symbol tAVAV/ tWC tAVWL/ tAS tWLAX/ tAH tDVWH/ tDS tWHDX/ tDH tWHGL tGHWL tELWL/ tCS tWHEH/ tCH tWLWH/ tWP 28F010/28F020 AC Characteristics--28F020--Write/Erase/Program Only Operations(1) Commercial and Extended Temperature Products Versions Characteristics Write Cycle Time Address Set-Up Time Address Hold Time 5 Data Set-Up Time 5 Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Chip Enable Set-Up Time before Write Chip Enable Hold Time Write Pulse Width 5 2 Notes 28F020-90(4) Min 90 0 40 55 40 55 10 6 0 15 0 40 55 20 3 3 2 10 9.5 1 40 55 10 6 0 15 0 60 55 20 10 9.5 1 20 10 9.5 1 ns s ms s 10 6 0 15 0 60 ns s ns ns ns ns 40 ns Max 28F020-120(4) 28F020-150(4) Min 120 0 40 Max Min 150 0 40 Max Unit ns ns ns tWHWL/ tWPH tWHWH1 tWHWH2 tVPEL Write Pulse Width High Duration of Programming Operation Duration of Erase Operation VPP Set-Up Time to Chip Enable Low NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Guaranteed by design. 3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 4. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics. 5. Minimum Specification for Extended Temperature product. 39 28F010/28F020 E 290207-13 290207-15 Figure 9. 28F010 Typical Programming Capability Figure 11. 28F010 Typical Erase Capability 290207-14 290207-16 Figure 10. 28F010 Typical Program Time at 12 V 40 Figure 12. 28F010 Typical Erase Time at 12 V E 28F010/28F020 0245_13 0245_11 Figure 13. 28F020 Typical Programming Capability NOTE: Does not include Pre-Erase Program. Figure 15. 28F020 Typical Erase Capability 0245_14 0245_12 NOTE: Does not include Pre-Erase Program. Figure 14. 28F020 Typical Program Time at 12 V Figure 16. 28F020 Typical Erase Time at 12 V 41 28F010/28F020 E 290207-10 Figure 17. AC Waveforms for Programming Operations 42 E 28F010/28F020 290207-11 Figure 18. AC Waveforms for Erase Operations 43 28F010/28F020 4.16 AC Characteristics--28F010--Alternative CE#-Controlled Writes(1) Commercial and Extended Temperature Versions 28F010-90(2) Notes Min 90 0 45 3 60 35 3 50 10 6 4 0 0 0 45 3 60 20 5 5 4 10 9.5 1 20 10 9.5 1 20 10 9.5 1 10 6 0 0 0 70 10 6 0 0 0 70 45 45 Max E Max Unit ns ns ns ns ns s ns ns ns ns 28F010-120(2) 28F010-150(2) Min 120 0 55 Max Min 150 0 55 Symbol tAVAV tAVEL tELAX Characteristic Write Cycle Time Address Set-Up Time Address Hold Time tDVEH Data Set-Up Time tEHDX tEHGL tGHWL tWLEL tEHWH tELEH Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Write Enable Set-Up Time before Chip Enable Write Enable Hold Time Write Pulse Width tEHEL tEHEH1 tEHEH2 tVPEL Write Pulse Width High Duration of Programming Operation Duration of Erase Operation VPP Set-Up Time to Chip Enable Low ns s ms s NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. See AC Input/Output Waveform and AC Testing Load Circuit for testing characteristics. 3. Minimum specification for extended temperature product. 4. Guaranteed by design. 5. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification. 44 E 4.17 Symbol tAVAV tAVEL tELAX tDVEH tEHDX tEHGL tGHWL tWLEL tEHWH tELEH 28F010/28F020 AC Characteristics--28F020--Alternate CE# Controlled Writes(1) Commercial and Extended Temperature Products Versions Characteristics Write Cycle Time Address Set-Up Time Address Hold Time 5 Data Set-Up Time 5 Data Hold Time Write Recovery Time before Read Read Recovery Time before Write Write Enable Set-Up Time before Chip Enable Write Enable Hold Time Write Pulse Width 5 2 Notes 28F020-90(4) Min 90 0 50 60 40 50 10 6 0 0 0 50 60 20 3 3 2 10 9.5 1 Max 28F020-120(4) 28F020-150(4) Min 120 0 55 60 45 50 10 6 0 0 0 60 60 20 10 9.5 1 20 10 9.5 1 ns s ms s 10 6 0 0 0 70 ns s ns ns ns ns 45 ns Max Min 150 0 55 Max Unit ns ns ns tEHEL tEHEH1 tEHEH2 tVPEL Write Pulse Width High Duration of Prog. Operation Duration of Erase Operation VPP Set-Up Time to Chip Enable Low NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Guaranteed by design. 3. The integrated stop timer terminates the programming/erase operations, thus eliminating the nee for a maximum d specification. 4. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics. 5. Minimum specification for extended temperature product. 45 28F010/28F020 4.18 Erase and Programming Performance Parameter Notes Min Typical 28F010 28F020 2 4 28F010 10 12.5 Max E Unit 28F020 30 25 Sec Sec Chip Erase Time Chip Program Time 1, 3, 4 1, 2, 4 1 2 NOTES: 1. "Typicals" are not guaranteed, but based on samples from production lots. Data taken at 25 C, 12 V VPP. .0 2. Minimum byte programming time excluding system overhead is 16 sec (10 sec program + 6 sec write recovery), while maximum is 400 sec/byte (16 sec x 25 loops allowed by algorithm). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. Excludes 00H programming prior to erasure. 4. Excludes system level overhead. 290207-19 NOTE: Alternative CE#-Controlled Write Timings also apply to erase operations. Figure 19. Alternate AC Waveforms for Programming Operations 46 E 5.0 28F010/28F020 ORDERING INFORMATION E2 8 F0 1 0 - 1 2 0 Operating Temperature T = Extended Temp Blank = Commercial Temp Package P = 32-Pin PDIP N = 32-Lead PLCC E = 32-Lead TSOP Product Line Designator for all Intel Flash products Access Speed (ns) Density 010 = 1 Mbit 290207-20 1M VALID COMBINATIONS: E28F010-90 N28F010-90 E28F010-120 N28F010-120 E28F010-150 N28F010-150 TE28F010-90 TE28F010-120 TE28F010-150 TN28F010-90 TN28F010-120 TN28F010-150 N28F020-90 N28F020-120 N28F020-150 TN28F020-90 TN28F020-120 TN28F020-150 P28F010-90 P28F010-120 P28F010-150 TP28F010-90 TP28F010-120 TP28F010-150 P28F010-90 P28F010-120 P28F010-150 2M E28F020-90 E28F020-120 E28F020-150 TE28F020-90 TE28F020-120 TE28F020-150 6.0 ADDITIONAL INFORMATION Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools. 47 |
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